1Technical Field
The present invention relates generally to phase locked loop circuitry; and, more particularly, to phase locked loop circuitry employing current controlled oscillators
2Related Art
Conventional phase locked loop technologies commonly suffer from a necessity for precision components to operate in a substantially predictable and stable manner. Where such precision components are available, conventional technologies operate with sufficient reliability as dictated by present industrial standards. However, the direction of much of the semiconductor industry is towards cheaper and more embedded components that typically suffer from poor tolerances. For example, it is not uncommon for particular component values in many phase locked loops to vary as great as plus or minus 50% of the predetermined and expected component value. Additionally, environmental perturbations having relatively long time constant responses, including temperature variations and aging of the components, among other perturbations, may result in a drift of particular components values over time within a conventional phase locked loop.
Other real time perturbations having significantly shorter time constant responses, such as electromagnetic interference and radio frequency interference, as well as intrinsic parasitics within an integrated circuit, among others electrical and magnetic perturbations, may result in dynamic component value change. In other words, the dynamic range over which the individual components may drift as a function of time may result in undesirable performance degradation of the conventional phase locked loop. Such effects are undesirable, in that, they can result in the drift of the center operating frequency at which the phase locked loop is intended to operate. There is commonly a trade-off of stability in operation, as well as a trade-off of precision in center frequency tuning, that is governed by the imprecision of the individual components available for phase locked loops.
FIG. 1 is a system diagram illustrating a conventional embodiment of a prior art phase locked loop 100. A reference frequency signal is fed into a phase/frequency detector (PFD) 110. The phase/frequency detector (PFD) 110 provides an error signal using an output that is fed into at least one charge pump. In the conventional embodiment 100 of a prior art phase locked loop, a charge pump 120 and a charge pump 170 are provided with the error signal generated by the phase/frequency detector (PFD) 110. The charge pump 120 and the charge pump 170 are both fed into low pass filter circuitry 130. The low pass filter circuitry 130 additionally contains integrating circuitry 132. A center frequency current generator 140 provides an initial candidate current for the conventional embodiment 100 of a prior art phase locked loop. The center frequency current generator 140 initially feeds a current controlled oscillator (ICO) 150 that generates an original candidate frequency. The original candidate frequency is scaled using a divider (.div.N) 160, and the resultant is returned as a feedback frequency signal to the phase/frequency detector (PFD) 110. This feedback frequency signal completes the closed loop of the conventional embodiment 100 of a prior art phase locked loop.
The conventional embodiment of a prior art phase locked loop 100 typically suffers from deleterious operational effects stemming primarily from the variations of component values. Commonly, the center frequency current generator 140 is employed using a pull-up resistor coupled to a voltage source, known well to those having skill in the art of electronic and semiconductor devices. A poor tolerance/precision of the pull-up resistor can result in a initial candidate frequency that differs substantially from that frequency to which the conventional embodiment of a prior art phase locked loop 100 will eventually lock. Both the precision of the pull-up resistor and any additional imprecision of individual components that are used within the integrating circuitry 132 can accentuate instability and poor performance of operation within the conventional embodiment of a prior art phase locked loop 100. Ideally, the integrating circuitry 132 is used to perform compensation for any imprecise operation of the center frequency current generator 140.
Various conventional methods known to those having skill in the art of electronic and semiconductor devices for performing the integration of the integrating circuitry 132 are envisioned in the conventional embodiment of a prior art phase locked loop 100. Each of these conventional methods suffers from unique deleterious operation. Typical conventional embodiments commonly do not employ baseline components in the stead of precision components within the integrating circuitry 132. Baseline components include those components that are at the lowest possible tolerance/precision that may still be used for operation within the conventional embodiment of a prior art phase locked loop 100. Such baseline components are employed in electronic devices where low cost is a rigid design constraint. For example, a baseline capacitor may be obtained from the use of a metal oxide semiconductor field effect transistor (MOSFET). The capacitor component value of such an intrinsic device may vary across a relatively large percentage of its nominal value when biased across a relatively small operational voltage range.
When such a baseline capacitor is employed in the integrating circuitry 132, a potentially poor selection of the initial candidate center frequency, as determined by the center frequency current generator 140, cannot be adequately compensated to bring it into line with a desired center frequency. For example, when both the pull-up resistor of the center frequency current generator 140 has a relatively poor tolerance/precision and the baseline capacitor employed in the integrating circuitry 132 similarly suffers in precision for, among other reasons, those stated above for baseline components, the total operation of the conventional embodiment of a prior art phase locked loop 100 may become unstable. This instability may occur when the baseline capacitor, as employed in the integrating circuitry 132, does not possess sufficient dynamic range to compensate for the imprecision of the initial candidate frequency as governed by the center frequency current generator 140. The integrating circuitry 132 of the conventional embodiment of a prior art phase locked loop 100 cannot sufficiently tune in response to the imprecision of the pull-up resistor within the center frequency current generator 140. This instability may be viewed as having a cascading effect whose total effect is contributed by the individual component imprecision within various circuitry within the entire phase locked loop.
For certain embodiments of integrating circuitry 132 that do possess sufficient tuning capability to compensate for imprecision of a pull-up resistor employed in the center frequency current generator 140, any undesirable dynamic range limitations may be imposed upon any supporting circuitry that feeds the integrating circuitry 132. In the conventional embodiment of a prior art phase locked loop 100 illustrated in FIG. 1, the charge pump 170 would receive the imposition of dynamic range constraints to provide stable operation of the phase locked loop. In other words, the unstable operation generated by imprecision of the pull-up resistor employed in the center frequency current generator 140 is undesirably cascaded through the compensating circuitry of the entire conventional embodiment of a prior art phase locked loop 100.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one skilled in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.